1. Field of the Invention
The present invention relates to a logic circuit structure. More particularly, the present invention relates to a bulk input current switch logic circuit.
2. Description of Related Art
As functions of electronic products trend to be more complicated, digital logic circuits become favorite choices for designers. Moreover, with quick development of process capability, nanometer process is implemented. In this case, processing technique originally bottlenecked development of digital circuits is now no longer the biggest problem, instead, it is the transmission speed of a conventional logic gate circuit that limits a whole circuit performance thereof.
FIG. 1 illustrates a circuit diagram of a 3-input NOR gate circuit of a conventional static logic circuit. For such conventional logic gate circuit, if input terminals A˜C are all level “0”, three P-type transistors are then turned on, so that an output V0 has a high level “1”. If at least one of the input terminals A˜C has the high level “1”, at least one N-type transistor is then turned on; so that the output V0 has a low level “0”. Since such logic circuit requires a set of serially connected P-type transistors (or N-type transistors), the more the input terminals are, during one output transition, the more the transistors required to be turned on.
FIG. 2 illustrates a circuit diagram of a 2-input NAND gate circuit of a conventional dynamic logic circuit. Such conventional dynamic logic circuit requires a pre-charge enable signal φ. Wherein, when the pre-charging enable signal φ has the low level “0”, the output V0 may be pre-charged to the high level “1”. When the pre-charge enable signal φ is transited to the high level “1”, the output V0 is then determined according to levels of the input B and input C. If the input B and the input C are all the high level “1”, the output V0 is then lowered to the level “0” due to turning on of the transistor. Conversely, if at least one of the input B and the input C is not the high level “1”, the output V0 is then maintained to be the high level “1”.
Next, referring to FIGS. 3A and 3B, FIG. 3A is a circuit diagram illustrating a conventional N-type transistor differential logic circuit. FIG. 3B is an sample diagram of a logic unit 310 of FIG. 3A. Such conventional logic circuit may implement a differential input via input A, input B or input C, and inverted signal input Ā, input B or input C. In coordination with a conventional technique of the dynamic logic circuit, a pre-charge phase is controlled via the pre-charge enable signal φ. Moreover, the conventional logic circuit may further include a latch circuit (in coordination with a transistor MP1 of an output Q, or a transistor MP2 of an output Q) for further stabilizing the output of the circuit. However, the differential logic circuit also requires a set of serially connected transistor in case of multiple inputs.
FIG. 4 is a circuit diagram illustrating a conventional bulk input differential logic circuit. Referring to FIG. 4, via a current sense amplifier composed of transistors M2, M3, M5 and M7, such conventional logic circuit may sense a current IL generated by transistors M41˜M4n, connected in parallel, and sense a current IR generated by transistors M81˜M8n, connected in parallel, and meanwhile generate the output Q and the Q output according to the sensing results. The pre-charge enable signal φ and the transistors M1 and M6 respectively provide a pre-charge signal and a pre-charge path. The transistor M9 provides a ground voltage during a non pre-charge period. Regardless of the number of the input terminals, such conventional logic circuit only has 3 serially connected N-type transistors, and therefore a response speed of the circuit may be effectively improved.